layout.lds (1025B)
1 /* 2 2018 David DiPaola 3 licensed under CC0 (public domain, see https://creativecommons.org/publicdomain/zero/1.0/) 4 */ 5 6 /* code entry point */ 7 ENTRY(main) 8 9 /* memory regions (see QEMU:vexpress.c) */ 10 MEMORY { 11 MAP_IO_UART0 : ORIGIN = 0x1C090000, LENGTH = 0x00000400 /* 1KB */ 12 MAP_DRAM : ORIGIN = 0x80000000, LENGTH = 0x80000000 /* 2GB */ 13 } 14 15 /* ELF binary sections */ 16 SECTIONS { 17 /* NOTE `SUBALIGN` is used with the `gcc` flags `-ffunction-sections` and `-fdata-sections` to ensure each function and piece of data are properly aligned */ 18 19 /* IO: UART0 */ 20 SECTION_IO_UART0 ORIGIN(MAP_IO_UART0): SUBALIGN(4) { 21 *(.data) 22 *(.bss) 23 } >MAP_IO_UART0 24 25 /* DRAM */ 26 .text ORIGIN(MAP_DRAM) + 0 : SUBALIGN(4) { /* code and read-only data */ 27 *(.text.startup.main) 28 *(.text) 29 *(.rodata) 30 } >MAP_DRAM 31 .data ORIGIN(MAP_DRAM) + SIZEOF(.text) : SUBALIGN(4) { /* initialized data */ 32 *(.data) 33 } >MAP_DRAM 34 .bss ORIGIN(MAP_DRAM) + SIZEOF(.text) + SIZEOF(.data) : SUBALIGN(4) { /* uninitialized data */ 35 *(.bss) 36 } >MAP_DRAM 37 38 } 39